Along with a constantly increasing packing density of integrated semiconductor devices, the reduction of the size of the single cells of static memory arrays, the attendant decrease of the operating current levels and the consequent magnified influence of parasitic electric factors of the integrated structures impose the use of a reading circuitry having an enhanced precision and reliability while ensuring a high speed. The use of differential sense amplifiers compensates for the effects due to "process spread", temperature and supply voltage variations as common mode contributions. Moreover modulated-current offset type as well as current-unbalance type sense amplifiers permit to free the sensing behavior from the maximum value that the supply voltage may reach, besides simplifying the dimensioning of transistors which form the sense amplifier in respect to the alternative load-unbalance system.
Usually the required control of the output common mode of the high gain differential sense amplifier is conveniently implemented by using an output latch wherein the extracted (read or sensed) datum may be stored. Moreover it is normal practice to prevent power consumption during standby periods by interrupting the various current paths between the supply rails of the circuit and by reestablishing correct bias conditions of the sensing circuit during a first preliminary phase of a reading cycle before evaluating the datum stored through a first discriminating step immediately followed by an amplifying step and by a storing step of the extracted datum in an output latch. The distinct phases of a complete reading cycle for a datum stored in a selected memory cell are controlled by means of a plurality of timing signals. A sense amplifier with these characteristics is relatively complex and remains sensitive to noise. In a prior application, U.S. Ser. No. 07/878,823, filed on May 4, 1992, the applicant of which is also an applicant of the present application, an improved sense amplifier is disclosed wherein the loads of the two lines of the input network of the sensing differential amplifier are cross coupled to the input pair of transistors of the differential amplifier in order to form also an output latch circuit for storing the extracted datum. Basically, in the sense amplifier object of this prior application, the same load elements of the two branches or lines of the input network of the sensing differential amplifier are identical and constitute also the loads of the input pair of transistors of the differential amplifier and are cross coupled thereto in order to constitute, together with the same pair of input transistors of the differential amplifier, an output latch circuit for storing an extracted datum.
The circuit is controlled by means of three timing signals and utilizes two control circuits (NOR gates), each having two inputs and an output and which may be preferably in the form of a cascode circuit. The signal present on a respective line of the input network of the differential amplifier is fed to an input of these cascode-type control circuits, while at the other input a first of said control signals is applied for enabling the cascode circuit to generate on its output node an amplified replica of the signal present on said first input. The output signal of the cascode circuit is utilized for enabling/disabling precharge and/or charge current paths through the respective line of said input network.
Any sense amplifier system has a limited sensitivity and therefore there is a lower limit of differential signals below which the sense amplifier may fail to discriminate between an erased or a programmed cell. What is desirable is a differential input signal of sufficiently high amplitude which will permit the sense amplifier (also called a differential amplifier or comparator) to perform a level discrimination reliably and thereafter amplify the differential signal for producing through an output the extracted information, eventually storing it in an output latch circuit.
Another problem in the prior act is overshoot. As in any capacitance charging process, the conditions suitable for carrying out a reliable comparison step are reached only after transient phenomena have decayed. For example, a fast precharge phase is followed by a recovery period during which decay of overshoots or dampening of eventual oscillations of the potential on the input nodes of the comparator, e.g. on the connection node between the selected bitline and the relative load, as well as of the potential which developes on the output node of the cascode circuits controlling the current paths, takes place.
These overshoots, e.g. an excessive drop of potential on the output nodes of the cascode circuits toward ground potential during an initial transient of a precharge phase, may cause a cut-off of the load transistor and, if the ensuing recovery period is not sufficiently short, an erroneous evaluation of the datum by the comparator may occur. Such a transient recovery phase for the attainment of stable conditions of the reference system should also last for the shortest time as possible in order to reduce the time necessary for completing a reading cycle.